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产品CDCLVD1204TI
描述

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 IN1) to 4 pairs of differential LVDS clock outputs (OUT0 OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS LVPECL or LVCMOS.

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