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产品CDCLVP2106TI
描述

The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.

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制造商型号分类描述下载
JST Sales America Inc

JST Sales Ameri...

04FFS-SP-TF(LF)...连接器FFC,FPC(扁平柔性)连接...conn fcc 4pos r/a smd 1.25mm